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By Zhiqiang Li

This publication normally makes a speciality of decreasing the excessive parasitic resistance within the source/drain of germanium nMOSFET. With  adopting of the Implantation After Germanide (IAG) approach, P and Sb co-implantation procedure and a number of Implantation and a number of Annealing (MIMA) procedure, the electron Schottky barrier peak of NiGe/Ge touch is modulated to 0.1eV, the thermal balance of NiGe is more suitable to six hundred℃ and the touch resistivity of metal/n-Ge touch is tremendously lowered to 3.8×10−7Ω•cm2, respectively. along with, a discounted  source/drain parasitic resistance is validated within the  fabricated Ge nMOSFET. Readers will locate worthy information regarding the source/drain engineering strategy for high-performance CMOS units at destiny expertise node.

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